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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, 2001 zarlink semiconductor inc. all rights reserved. features ? fax and modem interface (v.34/v.34+) ? designed to work at da ta rates up to 56kbits ? external programmable line and network balance impedances ? programmable dc termination characteristics ? iec950 recognised component ? transformerless 2-4 wire conversion ? integral loop switch ? dial pulse and dtmf operation ? accommodates parallel phone detection ? line state detection outputs: -loop current/ringing voltage/line voltage ? +5v operation, low on-hook power (25mw) ? full duplex voice and data transmission ? on-hook reception from the line ? meets french current limit requirements ? conforms to german dial pulse standards ? approvable to ul 1950 ? industrial temperature range available applications ? interface to central office or pabx line for: ? fax/modem ? electronic point of sale ? security system ? telemetry ?set top boxes description the zarlink MH88437 data access arrangement (d.a.a.) provides a complete interface between audio or data transmission equipment and a telephone line. all functions are integrated into a single thick film hybrid module which provides high voltage isolation, very high reliability and optimum circuit design, needing a minimum of external components. the impedance and network balance are externally programmable, as are the dc termination characteristics, ma king the device suitable for most countries worldwide. september 2003 ordering information MH88437ad-p 28 pin dil package MH88437as-p 28 pin sm package MH88437as-pr 28pin sm package (tape & reel) 0 c to +70 c MH88437-p data access arrangement data sheet figure 1 - functional block diagram opto- isolation logic input buffer isolation isolation isolation analog buffer analog buffer buffer thl cancellation impedance matching circuit isolation barrier vcc agnd lc vr+ vx rv tip ring user connections network connections input buffer & vloop1 ring & loop line termination vloop2 vr- nb1 nb2 loop lcd za rs vbias and line cl
MH88437-p data sheet 2 zarlink semiconductor inc. figure 2 - pin connections pin description pin # name description 1nb1 network balance 1. external passive components must be connected between this pin and nb2. 2nb2 network balance 2. external passive components must be connected between this pin and nb1. 3vr+ differential receive (input). analog input from modem/fax chip set. 4vr- differential receive (input). analog input from modem/fax chip set. 5vx transmit (output). ground referenced (agnd) output to modem/fax chip set, biased at +2.0v. 6lc loop control (input). a logic 1 applied to this pin activates internal circuitry which provides a dc termination across tip and ring. this pin is also used for dial pulse application. 7za line impedance. connect impedance matching components from this pin to ground (agnd). 8agnd analog ground. 4-wire 0v reference connect to mains earth (ground). 9v cc positive supply voltage . +5v. 10 vbias internal reference voltage. +2.0v reference voltage. this pin should be decoupled externally to agnd, typically with a 10 f 6.3v capacitor . 11 loop loop (output). the output voltage on this pin is proportional to the line voltage across tip - ring, scaled down by a factor of 50. 12, 14 ic internal connection. no connection should be made to this pin externally. 13 rs ringing sensitivity. connecting a link or resistor between this pin and loop (pin 11) will vary the ringing detection sensitivity of the module. 15 lcd loop condition detect (output). indicates the status of loop current. 16 rv ringing voltage detect (output). the rv output indicates the presence of a ringing voltage applied across the tip and ring leads. cl ic lc c1 tip agnd ring rv za vx vr- vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vr+ nb1 nb2 vbias loop ic rs ic vloop1 vloop2 c2 sc sc np np lcd
MH88437-p data sheet 3 zarlink semiconductor inc. functional description the device is a data access arrangement (d.a.a.). it is used to correctly terminate a 2-wire telephone line. it provides a signalling link and a 2-4 wire line interface between an analog loop and subscriber data transmission equipment, such as modems, facsimiles (fax?s), remote me ters, electronic point of sale equipment and set top boxes. isolation barrier the device provides an isolation barrier capable of meeting the supplementary barrier requirements of the international standard iec 950 and the national vari ants of this scheme such as en 60950 for european applications and ul 1950 for north american applications. external protection circuit an external protection circuit assists in preventing damage to the device and the subscriber equipment, due to over-voltage conditions. see application note msan-154 for recommendations. suitable markets the MH88437 has features such as programmable li ne and network balance im pedance, programmable dc termination and a supplementary isolation barrier. for countries that do not need to meet the french and german requirements there is a pin for pin compatible device the mh88435. there are, however, a small number of countries with a 100m ? leakage requirement that this device does not meet. these are belgium, greece, italy, luxembourg, spain and poland. ctr21 is generally accepted within europe, and this route should be selected for those countries. this should be attempted with the consultation of a local approvals house. approval specifications are regularly changing and the relevant specification should always be consulted before commencing design. 17 cl current limit. a logic 0 applied to this pin activates internal circuitry which limits the loop current. 18 np no pin. isolation barrier, fitted, no pin fitted in this position. 19 np no pin . isolation barrier, no pin fitted in th is position 20 ic internal connection. no connection should be made to this pin externally. 21,22 sc short circuit. these two pins should be connected to each other via a 0 ? link. 24 vloop2 loop voltage control node 2. used to set dc termination characteristics. 25 vloop1 loop voltage control node 1. used to set dc termination characteristics. 27 ring ring lead. connects to the ?ring? lead of the telephone line. 28 tip tip lead. connects to the ?tip? lead of the telephone line. 26,23 c1, c2 cap . fit a 22nf cap between these two pins. pin description pin # name description
MH88437-p data sheet 4 zarlink semiconductor inc. line termination when loop control (lc) is at a logic 1, a line termination is applied across tip and ring. the device can be considered off-hook and dc loop current will flow. the line termination consists of both a dc line termination and an ac input impedance. it is used to terminate an incoming call, seize the line for an outgoing call, or if it is applied and disconnected at the required rate, can be used to generate dial pulses. the dc termination resembles approximately 300 ? resistance, which is loop current dependent. furthermore, it can be programmed to meet different national requirements. for normal operation vloop3 should be open circuit and a resistor (r2) should be fitted between vloop1 and vloop2, as shown in figure 4. the approval specification will give a dc mask characteri stic that the equipment will need to comply to. the dc mask specifies the amount of current the daa can sink fo r a given voltage across tip and ring. graph 1 shows how the voltage across tip and ring varies with different resistors (r2) for a given loop current. by applying a logic 0 to pin 17, cl , the loop current will be limited to below 60ma as required in france and the european tbr21 specification. for all other coun tries where current limiting is not required, cl should be set to 1. figure 3 - dc programming capability iloop=15ma iloop=20ma iloop=26ma 35 30 10 5 0 25 20 15 40 50 150 250 350 450 550 650 750 850 950 r2(kohms) v(t-r)
MH88437-p data sheet 5 zarlink semiconductor inc. input impedance the ac input impedance should be set by the user to match the line impedance. the MH88437 has a programmable input impedance set by fitting external components between the za pin and agnd. for complex impedances the configuration shown in figure 4 (below) is most commonly found. figure 4 - complex impedances to find the external programming components for configuration 4, the following formula should be used: zext = [(10 x r1)-1k3]+[(10 x r2)//(c1/10)] e.g. if the required input impedance = 220 ? + (820 ? //115nf), the external network to be connected to za will be: za = 900 ? + (8k2 ? //12nf) where the input impedance (z) = 600r the equation can be simplified to: za = (10 x z) - 1k3 ? za = 4k7 ? note : a table of commonly used impedances can be found in the daa application?s document msan-154. where zext = external network connect ed between za and agnd and zint = 1.3k ? (internal resistance). network balance the network balance impedance of the device can be programmed by adding external components between nb1 and nb2. for countries where the balance im pedance matches the line impedance, a 16k ? resistor should be added between nb1 and nb2. ringing voltage detection the sensitivity of the ringing voltage detection circuitry ca n be adjusted by applying an external resistor (r7, figure 5) between the rs and loop pins. with a short circuit, the threshold sensitivity is ~10vrms, therefore r7 = 30k ? x (desired threshold voltage - 10vrms). example: 300k ? gives ~20vrms and 600k ? gives ~30vrms. an ac ringing voltage across tip and ring will cause rv to output ttl pulses at the ringing frequency, with an envelope determined by the ringing cadence. r1 r2 c1
MH88437-p data sheet 6 zarlink semiconductor inc. parallel phone and dummy ringer an external parallel phone or dummy ringer circuit can be connected across tip and ring as shown in figure 5. a dummy ringer is an ac load which represents a telephone?s mechanical ringer. in normal circumstances when a telephone is on-hook and connected to the pstn, its ac (ringer) load is permanently presented to the network. this condition is us ed by many ptt?s to test line continuity, by placing a small ac current onto the line and measuring the voltage across tip (a) and ring (b). today?s telecom equipment may not have an ac load present across tip and ring (e.g. modems), therefore any testing carried out by the ptt will see an open circuit across tip and ring. in this instance the ptt assumes that the line continuity has been damaged. to overcome this problem many ptt?s specify that a "d ummy ringer" is presented to the network at all times. ideally its impedance should be low in the audio band and hi gh at the ringing frequencies (e.g. 25hz). note that the requirement for the "dummy ringer" is country specific. parallel phone detection is used mostly in set-top box applications. this is when a modem call will need to be disconnected from the central office by the equipment when the parallel phone is in the off-hook state. this is to allow the subscriber to make emergency calls. to detect this state, additional circuitry will be required. refer to application note msan-154. 2-4 wire conversion the device converts the balanced 2-wire input, presented by the line at tip and ring, to a ground referenced signal at vx, biased at 2.0v. this simplifies the interface to a modem chip set. conversely, the device converts the differential signal input at vr+ and vr- to a balanced 2-wire signal at tip and ring. the device can also be used in a single ended mode at the receive input, by leaving vr+ open circuit and connecting the input signal to vr- only. both inputs are biased at 2.0v. during full duplex transmission, the signal at tip and ring consists of both the signal from the device to the line and the signal from the line to the device. the signal input at vr+ and vr- being sent to the line, must not appear at the output vx. in order to prevent this, the device has an intern al cancellation circuit, the measure of this attenuation is transhybrid loss (thl). the MH88437 has the ability to transmit analog signals fr om tip and ring through to vx when on-hook. this can be used when receiving caller line identification information. transmit gain the transmit gain of the MH88437 is the gain from the differential signal across tip and ring to the ground referenced signal at vx. the internal transmit gain of the device is fixed as shown in the ac electrical characteristics table. for the correct gain, the input im pedance of the MH88437, must match the specified line impedance. by adding an external potential divider to vx, it is possible to reduce the overall gain in the application. the output impedance of vx is approximately 10 ? and the minimum resistance from vx to ground should be 2k ? . example: if r3 = r4 = 2k ?, in figure 5, the overall gain would reduce by 6.0db. receive gain the receive gain of the MH88437 is the gain from the diff erential signal at vr+ and vr- to the differential signal across tip and ring. the internal receive gain of the device is fixed as shown in the ac electrical characteristics table. for the correct gain, the input impedance of the MH88437 must match the specified line impedance.
MH88437-p data sheet 7 zarlink semiconductor inc. with an internal series input resistance of 47k ? at the vr+ and vr- pins, external series resistors can be used to reduce the overall gain. overall receive gain = 0db+20log (47k ? /(47k ? +r5)). for differential applications r6 must be equal to r5 in figure 5. example: if r5 = r6 = 47k in figure 3, the overall gain would reduce by 6.0db. supervisory features the device is capable of monitoring the line conditions across tip and ring, this is shown in figure 5. the loop condition detect pin (lcd), indicates the status of the line. the lcd output is at logic 1 when loop current flows, indicating that the MH88437 is in an off hook state. lc d will also go high if a parallel phone goes off-hook. therefore, line conditions can be determined with the lc and the lcd pins. the loop pin output voltage vloop is proportional to the line voltage across tip and ring scaled down by a factor of 50 and offset by 2.0v(t-r). with the aid of a simple external detector the lc, lcd and loop pins can be used to generate the signals necessary for parallel phone operation, e.g. with a set top box. see msan-154 for further details. when the device is generating dial pulses, the lcd pin outputs ttl pulses at the same rate. the lcd output will also pulse if a parallel phone is used to dial and when ringing voltage is present at tip and ring. mechanical data see figures 12, 13 and 14 for details of the mechanical specification.
MH88437-p data sheet 8 zarlink semiconductor inc. figure 5 - typical application circuit . absolute maximum ratings* - all voltages are with respect to agnd unless otherwise specified. parameter sym min max units comments 1 dc supply voltage v cc -0.3 6 v 2 storage temperature t s -55 +125 c 3 dc loop voltage v tr -110 +110 v tip nb2 ring vx vr+ rv lc agnd vcc tip ring c2 +5v 9 8 6 16 5 3 28 analog input analog ringing voltage detect output loop control input MH88437 + output c4 c1 notes: r1 & c1: dummy ringer, country specific za 7 zext r2: dc mask resistor 82k ? typical r1 25 24 vloop1 vloop2 vr - 4 analog input r2 lcd 15 loop current detect output nb1 zb: network balance impedance r3 r5 r6 r4 r5 = r6: receive gain resistors typically 100k r3 & r4: transmit gain resistors 2k2 c3 + 10 vbias typically 0.39 f, 250v & 3k ? c2 & c3 = 10 f 6v c7 & c8 = 39nf for 12khz filter and 22nf for 16khz filter. these can be left off if meter pulse filtering not required. zext: external impedance d1 zener diode 9v1 (x2) l1, l2 = 4.7mh rdc<10 ?. these can be left off if meter pulse filtering not required. d1 c7 l1 l2 13 11 rs loop zb 1 2 c5 c6 c4, c5 & c6 = 1 f coupling capacitors r7 = 620k ? (30v rms ringing sensitivity) cl d2 d2 = teccor p2703 protection r7 = ground (earth) 21 22 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) c8 c9 = 22nf 14) c9 23 26
MH88437-p data sheet 9 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25c with nominal +5v supply and are for design aid only ? electrical characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c with nominal + 5v supplies and are for design aid only. note 1: low loop current operation depends on value of resistor connected between v loop 1 and v loop 2. note 2: this is equivalent to 10m ? leakage tip/ring to ground. note 3. refer to eia/tia 464 section 4.1.1.4.4 4 transient loop voltage v tr 300 v 1ms on hook 5 ringing voltage v r 150 vrms vbat = -56v 6 loop current i loop 60 90 ma ma cl =0 v tip-ring 40v cl =1 7 ring trip current i trip 180 marms 250ms 10% duty cycle or 500ms single shot recommended operating conditions parameter sym min typ ? max units test conditions 1 dc supply voltages v cc 4.75 5.0 5.25 v 2 operating temperatures industrial temperature t op 0 -40 25 70 +85 c 3 ringing voltage v r 75 90 vrms vbat = -48v loop electrical characteristics ? characteristics sym min typ ? max units test conditions 1 ringing voltage no detect detect vr 14 7 vrms vrms externally adjustable 2 ringing frequency 15 68 hz 3 operating loop current 15 60 80 ma ma cl =0 v tip-ring 40v cl =1 (see note 1) 4 off-hook dc voltage 6.0 6.0 7.8 v v v externally adjustable i loop =15ma) i loop =20ma) (note 3) i loop= 26ma) where r2 = 110k ? 5 leakage current (tip or ring to agnd) 10 7 a ma 100v dc (see note 2) 1000v ac 6 leakage current on-hook (tip to ring) 9 18 10 20 ? v bat (= -50v) v bat (= -100v) 7 dial pulse detection on off 0 0 +1 +1 +2 +2 ms ms dial pulse delay 8 loop condition detect threshold off-hook 5 16 v voltage across tip and ring absolute maximum ratings* - all voltages are with respect to agnd unless otherwise specified.
MH88437-p data sheet 10 zarlink semiconductor inc. ? electrical characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c with nominal + 5v supplies and are for design aid only. dc electrical characteristics ? characteristics sym min typ ? max units test conditions 1 supply current i cc 5mav dd (= 5.0v, on-hook) 2rv, lcd low level output voltage high level output voltage v ol v oh 2.4 0.4 v v i ol = 4ma i oh = 0.4ma 3 lc low level input voltage high level input voltage low level input current high level input current v il v ih i il i ih 2.0 0 350 0.8 60 400 v v a a v il = 0.0v v ih = 5.0v 4vr+ vr- dc common mode vcm 0 2 vcc vdc use coupling caps for higher voltages and single ended ac electrical characteristics ? characteristics sym min typ ? max units test conditions 1 input impedance vr- vr+ 47k 94k ? ? 2 output impedance at vx 10 ? 3 receive gain (vr to 2-wire) -1 0 1 db test circuit (figure 8) input 0.5v at 1khz 4 frequency response gain (relative to gain @ 1khz) -0.5 0 0.5 db iloop = 15-60ma 300hz to 3400 hz 5 signal output overload level at 2-wire at vx 0 0 dbm dbm thd < 5% @ 1khz i loop = 25-60ma vcc = 5v 6 signal/noise & distortion at 2-wire at vx sinad 70 70 db db input 0.5v at 1khz i loop = 25-60ma 300-3400hz 7 power supply rejection ratio at 2-wire at vx psrr 25 25 40 40 db db ripple 0.1vrms 1khz on v dd 8 transhybrid loss thl 16 25 db test circuit (figure 8) 300-3400hz at v r 9 2-wire input impedance zin note 3 ? @ 1khz 10 return loss at 2-wire (reference 600 ? ) rl 14 20 18 24 24 24 db db db test circuit (figure 9) 200-500hz 500-2500hz 2500-3400hz
MH88437-p data sheet 11 zarlink semiconductor inc. ? electrical characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c with nominal + 5v supplies and are for design aid only. 11 longitudinal to metallic balance metallic to longitudinal balance nc 46 46 60 40 58 53 db db db db test circuit (figure 10) 300-1000hz 1000-3400hz test circuit (figure 11) 200-1000hz 1000-4000hz 12 idle channel noise at 2-wire at vx at 2-wire at vx 15 15 -65 -65 20 20 dbrnc dbrnc dbm dbm cmess filter 300-3400hz filter 13 transmit gain (2-wire to vx) off-hook on-hook -1 0 0 +1 db db test circuit (figure 7) input 0.5v @ 1khz lc = 0v 14 frequency response gain (relative to gain @ 1khz) -0.5 -0.5 0 0 0.5 0.5 db db 300hz 3400hz 15 intermodulation distortion products at vx and 2w imd 75 db i loop = 25-60ma f1 = 1khz at -6dbm f2 = 800hz at -6dbm total signal power = -3dbm 16 distortion at vx due to near end echo (300hz - 3400hz bandwidth) 75 db i loop = 25-60ma f1 = 1khz at -6dbm f2 = 800hz at -6dbm total signal power = -3dbm 17 common mode rejection at vx cmr 50 db test circuit (figure 10) 1-100hz note 4 18 common mode overload cml 100v v pk-pk test circuit (figure 10) 1-100hz note 4 ac electrical characteristics ? (continued) characteristics sym min typ ? max units test conditions
MH88437-p data sheet 12 zarlink semiconductor inc. figure 6 - test circuit 1 figure 7 - test circuit 2 dut 3 4 5 25 vx agnd rv vr+ vr- tip nb1 ring 24 23 22 21 82k vloop1 lc 5v 1k vloop5 vloop4 c1 vloop2 vcc za nb2 10uf vbias 10 27 2 28 1 16k 616 8 7 9 4.7k loop rs lcd 11 13 15 iloop 5v + = ground (earth) 26 22nf c2 vs i=20ma 10h 500 ? -v 100uf 10h 500 ? + 100uf + gain = 20 * log (vx / vs) dut 3 4 5 25 vx agnd rv vr+ vr- tip nb1 ring 24 23 22 21 82k vloop1 lc 5v 1k vloop5 vloop4 c1 vloop2 vcc za nb2 10uf vbias 10 27 2 28 1 16k 6168 7 9 4.7k 5v loop rs lcd 11 13 15 impedance = zin + = ground (earth) c2 26 22nf
MH88437-p data sheet 13 zarlink semiconductor inc. figure 8 - test circuit 3 figure 9 - test circuit 4 100uf zin 10h 500 ? -v i=20ma 10h 500 ? 100uf + + gain = 20 * log (v(zin) / vs) dut 3 4 5 25 vx agnd rv vr+ vr- tip nb1 ring 24 23 22 21 82k vloop1 lc 5v 1k vloop5 vloop4 c2 vloop2 vcc za nb2 10uf vbias 10 27 2 28 1 16k 616 8 7 9 4.7k 5v loop rs lcd 11 13 15 vs + = ground (earth) 26 22nf c1 100uf -v 10h 500 ? i=20ma v1 300 ? 300 ? vs = 0.5v + 100uf + return loss = 20 * log (v1 / vs) 10h 500 ? zin dut 3 4 5 25 vx agnd rv vr+ vr- tip nb1 ring 24 23 22 21 82k vloop1 lc 5v 1k vloop5 vloop4 c2 vloop2 vcc za nb2 10uf vbias 10 27 2 28 1 16k 6168 7 9 4.7k loop rs lcd 11 13 15 5v + = ground (earth) 26 22nf c1
MH88437-p data sheet 14 zarlink semiconductor inc. figure 10 - test circuit 5 figure 11 - test circuit 6 100uf vs = 0.5v 300 ? 300 ? -v 10h 500 ? i=20ma + + 100uf long. to met. balance = 20 * log (v1 / vs) v1 10h 500 ? dut 3 4 5 25 vx agnd rv vr+ vr- tip nb1 ring 24 23 22 21 82k vloop1 lc 5v 1k vloop5 vloop4 c2 vloop2 vcc za nb2 10uf vbias 10 27 2 28 1 16k 6168 7 9 4.7k 5v loop rs lcd 11 13 15 cmr = 20 * log (vx / vs) + = ground (earth) 26 22nf c1 -v 10h 500 ? i=20ma 300 ? 300 ? v1 vs 100uf + 100uf + met. to long. balance = 20 * log (v1 / vs) 10h 500 ? 510 ? dut 3 4 5 25 vx agnd rv vr+ vr- tip nb1 ring 24 23 22 21 82k vloop1 lc 5v 1k vloop5 vloop4 c2 vloop2 vcc za nb2 10uf vbias 10 27 2 28 1 16k 6168 7 9 4.7k 5v loop rs lcd 11 13 15 + = ground (earth) 26 22nf c1
MH88437-p data sheet 15 zarlink semiconductor inc. figure 12 - mechanical data for 28 pin dil hybrid figure 13 - mechanical data for 28 pin surface mount hybrid notes: 1) not to scale 2) dimensions in inches. (dimensions in millimetres) 1.42 max (36.1 max) 0.162 max (4.12 max) 0.05 typ (1.27 typ) 0.020 + 0.005 (0.5 + 0.13) 0.063 max 0.260+ 0.015 (25.4 typ) 1.05 max (26.7 max) * dimensions to centre of pin. 1.00 typ 0.27 max (6.9 max) 0.08 typ (2 typ) 0.100+ 0.010 (2.54+ 0.25) * * 1 * (1.6 max) (6.6+ 0.38) 3) pin tolerances are non-accumulative. 4) recommended soldering conditions: wave soldering - max temp at pins 260 c for 10 secs. 0.300+ 0.010 (7.62+ 0.25) * notes: 1) not to scale 2) dimensions in inches. (dimensions in millimetres) 1.42 max (36.1 max) 0.162 max (4.11 max) 0.063 max * dimensions to centre of pin. 1 (1.6 max) 3) pin tolerances are non-accumulative. 4) recommended soldering conditions: 0.300+ 0.010 (7.62+ 0.25) * (25.15 typ) 0.060 typ (1.52 typ) 0.99 typ 0.9 + 0.015 (2.3 + 0.38) 0.265 max (6.73 max) 0.100+ 0.010 (2.54+ 0.25) * 0.020 + 0.005 (0.5 + 0.13) 0.05 typ (1.27 typ) * max reflow temp: 220 c for 10 secs. 1.15 max (29.2 max)
MH88437-p data sheet 16 zarlink semiconductor inc. figure 14 - recommended footprint for 28 pin surface mount hybrid 0.10 (2.54) 0.97 (24.64) 0.04 (1.02) 0.06 (1.52) 0.10 (2.54) 0.26 (6.60) notes: 1) not to scale 2) dimensions in inches. (dimensions in millimetres) 3) all dimensions are typical except * where marked with an. this gap is associated with the isolation barrier.
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